The design and realization of a new high speed FPGA-based chaotic true random number generator

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dc.contributor.authorKoyuncu, İsmail
dc.contributor.authorÖzcerit, Ahmet Turan
dc.date.accessioned2020-04-30T23:32:45Z
dc.date.available2020-04-30T23:32:45Z
dc.date.issued2017
dc.departmentDÜ, Düzce Meslek Yüksekokulu, Elektronik ve Otomasyon Bölümüen_US
dc.descriptionKOYUNCU, ismail/0000-0003-4725-4879en_US
dc.descriptionWOS: 000401384600016en_US
dc.description.abstractChaotic systems and chaos-based applications have been commonly used in the fields of engineering recently. The most essential part of them is the chaotic oscillator that has very critical role in some applications such as chaotic communications and cryptography. In this study, Sundarapandian-Pehlivan chaotic system has been modeled and simulated in three distinct platforms to show the advantages of FPGA-based chaotic oscillator with respect to alternative solutions. In the first stage, the chaotic system has been modeled numerically by the help of fourth order of Runge-Kutta (RK4) method. Additionally, phase portraits of the system have been obtained and Lyapunov exponents have been examined. Secondly, the system has been modeled by using PSpice for the implementation of the chaotic system with analog circuit elements. Then, Pspice simulation results have been compared with the numerical outcome to justify the designed model. Furthermore, the chaotic system has been physically confirmed with real analog circuit elements. Signals obtained from the physical system have been verified with both numerical and PSpice results. It has been also modeled by the help of method of RK4 in a hardware description language (VHDL) and the model further has been synthesized and tested for Xilinx Virtex-6 FPGA chip. Finally, the chaotic oscillator designed has been tested for True Random Number Generators (TRNG) and the maximum operating frequency has been achieved as 293 MHz with a speed of 58.76 Mbit/s. Besides, the random bit sets produced by TRNG have been further verified by FIPS-140-1 and NIST-800-22 statistical standards and it has been proved that the proposed design can be used in embedded cryptologic applications. (C) 2016 Elsevier Ltd. All rights reserved.en_US
dc.description.sponsorshipSakarya University Scientific Research Projects Commission PresidencySakarya University [2014-09-10001]en_US
dc.description.sponsorshipThis study was supported by the Sakarya University Scientific Research Projects Commission Presidency (No. 2014-09-10001).en_US
dc.identifier.doi10.1016/j.compeleceng.2016.07.005en_US
dc.identifier.endpage214en_US
dc.identifier.issn0045-7906
dc.identifier.issn1879-0755
dc.identifier.scopusqualityQ1en_US
dc.identifier.startpage203en_US
dc.identifier.urihttps://doi.org/10.1016/j.compeleceng.2016.07.005
dc.identifier.urihttps://hdl.handle.net/20.500.12684/4809
dc.identifier.volume58en_US
dc.identifier.wosWOS:000401384600016en_US
dc.identifier.wosqualityQ2en_US
dc.indekslendigikaynakWeb of Scienceen_US
dc.indekslendigikaynakScopusen_US
dc.language.isoenen_US
dc.publisherPergamon-Elsevier Science Ltden_US
dc.relation.ispartofComputers & Electrical Engineeringen_US
dc.relation.publicationcategoryMakale - Uluslararası Hakemli Dergi - Kurum Öğretim Elemanıen_US
dc.rightsinfo:eu-repo/semantics/closedAccessen_US
dc.subjectChaosen_US
dc.subjectChaotic oscillatorsen_US
dc.subjectField programmable gate array.en_US
dc.subjectRK4 algorithmen_US
dc.subjectTrue random number generatoren_US
dc.subjectNIST-800-22 statistical testsen_US
dc.titleThe design and realization of a new high speed FPGA-based chaotic true random number generatoren_US
dc.typeArticleen_US

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