Design and implementation of the FPGA-based chaotic van der pol oscillator

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dc.contributor.authorDursun, Mustafa
dc.contributor.authorKaşifoğlu, Elif
dc.date.accessioned2025-03-24T19:50:00Z
dc.date.available2025-03-24T19:50:00Z
dc.date.issued2018
dc.departmentDüzce Üniversitesi
dc.description.abstractIn this study, the chaotic Van der Pol system was implemented for real-time chaos applications on FPGA chip. The chaotic Van der Pol system was also modelled numerically by using the Euler algorithm ODE (Ordinary Differential Equation) solver on Matlab. Numerical structure of the chaotic Van der Pol oscillator designed on Matlab was taken as reference for the design of FPGA-based chaotic Van der Pol oscillator unit. The chaotic Van der Pol system was coded in Very High-Speed Integrated Circuits Hardware Description Language (VHDL) with 32-bit IEEE-754-1985 floating point number standard. The designed chaotic Van der Pol system was synthesized in the Xilinx ISE Project Navigator program and was implemented on the Xilinx VIRTEX-6 chip family, XC6VLX75T device, FF784 package. The maximum operating frequency of the FPGA-based chaotic Van der Pol oscillator unit obtained from Place and Route processes was 498.728 MHz. Additionally, chip statistics of the FPGA-based Van der Pol oscillator were presented.
dc.identifier.endpage314
dc.identifier.issn2618-575X
dc.identifier.issue3
dc.identifier.startpage309
dc.identifier.urihttps://hdl.handle.net/20.500.12684/19415
dc.identifier.volume2
dc.language.isoen
dc.publisherCeyhun YILMAZ
dc.relation.ispartofInternational Advanced Researches and Engineering Journal
dc.relation.publicationcategoryMakale - Ulusal Hakemli Dergi - Kurum Öğretim Elemanı
dc.rightsinfo:eu-repo/semantics/openAccess
dc.snmzKA_DergiPark_20250324
dc.subjectFPGA Chips|Van Der Pol Oscillator|VHDL|Euler Algorith|Chaotic Systems
dc.titleDesign and implementation of the FPGA-based chaotic van der pol oscillator
dc.typeArticle

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