Real Time Hardware Implementation of the 3D Chaotic Oscillator which having Golden-Section Equilibra
| dc.contributor.author | Tuna, Murat | |
| dc.contributor.author | Fidan, Can Bülent | |
| dc.contributor.author | Koyuncu, İsmail | |
| dc.contributor.author | Pehlivan, İhsan | |
| dc.date.accessioned | 2020-04-30T23:31:34Z | |
| dc.date.available | 2020-04-30T23:31:34Z | |
| dc.date.issued | 2016 | |
| dc.department | DÜ, Düzce Meslek Yüksekokulu, Elektronik ve Otomasyon Bölümü | en_US |
| dc.description | 24th Signal Processing and Communication Application Conference (SIU) -- MAY 16-19, 2016 -- Zonguldak, TURKEY | en_US |
| dc.description | Tuna, Murat/0000-0003-3511-1336; FIDAN, CAN BULENT/0000-0001-5252-6301 | en_US |
| dc.description | WOS: 000391250900304 | en_US |
| dc.description.abstract | In this study, the continuous-time, autonomous, 3D chaotic system having golden-section equilibra which is recently presented in the literature is implemented firstly as discrete time on an FPGA. In this design, the 3D chaotic system was programmed in 32-bit IQ-Math (16I-16Q) fixed-point number format using VHDL and Heun algorithm. The designed system has been synthesized and tested, using Xilinx ISE design tool, on Virtex-6 FPGA chip. According to the test results, operation frequency of the FPGA-based new chaotic signal generator is certain as 406.736MHz. In addition, chip statistics and performance results of the new chaotic oscillator are presented after the "Route&Place" processes performed on Xilinx ISE design tool. The chaotic oscillator design realized with fixed-point number format on FPGA has been shown to be use lesser chip hardware and higher operating frequency compared to the floating-point standard. | en_US |
| dc.description.sponsorship | IEEE, Bulent Ecevit Univ, Dept Elect & Elect Engn, Bulent Ecevit Univ, Dept Biomed Engn, Bulent Ecevit Univ, Dept Comp Engn | en_US |
| dc.identifier.endpage | 1312 | en_US |
| dc.identifier.isbn | 978-1-5090-1679-2 | |
| dc.identifier.startpage | 1309 | en_US |
| dc.identifier.uri | https://hdl.handle.net/20.500.12684/4313 | |
| dc.identifier.wosquality | N/A | en_US |
| dc.indekslendigikaynak | Web of Science | en_US |
| dc.language.iso | tr | en_US |
| dc.publisher | Ieee | en_US |
| dc.relation.ispartof | 2016 24Th Signal Processing And Communication Application Conference (Siu) | en_US |
| dc.relation.publicationcategory | Konferans Öğesi - Uluslararası - Kurum Öğretim Elemanı | en_US |
| dc.rights | info:eu-repo/semantics/closedAccess | en_US |
| dc.subject | Chaos | en_US |
| dc.subject | Chaotic system | en_US |
| dc.subject | FPGA | en_US |
| dc.subject | VHDL | en_US |
| dc.title | Real Time Hardware Implementation of the 3D Chaotic Oscillator which having Golden-Section Equilibra | en_US |
| dc.type | Conference Object | en_US |
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