Yazar "Tuna, Murat" seçeneğine göre listele

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  • Küçük Resim
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    Artificial Neural Network-Based 4-D Hyper-Chaotic System on Field Programmable
    (2020) Koyuncu, Ismail; Alcin, Murat; Erdogmus, Pakize; Tuna, Murat
    In this presented study, a 4-D hyper-chaotic system newly proposed to the literature, has been implemented as Multi-Layer Feed-Forward Artificial Neural Network-based on FPGA chip with 32-bit IEEE-754-1985 floating-point number standard to be utilized in real time chaos-based applications. In the first step of the study, 4-D hyper-chaotic system has been numerically modeled on FPGA using Dormand-Prince numeric algorithm. In the second step,the data set (4X10,000) obtained from Matlab-based numeric model has been divided into two parts as training data set (4X8,000) and test data set (4X2,000) to create ANN-based 4-D hyper-chaotic system. A Multi-Layer Feed-Forward ANN structure with 4 inputs and 4 outputs has been constructed for ANN-based 4-D hyper-chaotic system. This structure has only one hidden layer and there are 8 neurons having Tangent Sigmoid activation function used as the activationfunction in each neuron.2.58E-07 Mean Square Error (MSE) value has been obtained from the training of ANN-based 4-D hyper-chaotic system. In the third step, after the successful training of ANN-based 4-D hyper-chaotic system, the design of ANN-based 4-D hyper-chaotic system has been carried out on FPGA by taking the bias and weight values of the ANN structure as reference. In this step, at first, Matlab-based Feed-Forward Multi-Layer 4X8X4 network structure has been coded in Very High Speed Integrated Circuit Hardware Description Language (VHDL) to be implemented on FPGA chips. Then, the bias and weight values of the ANN structure has been converted from decimal number system to floating-point number standard and these converted values have been embedded into the network structure.In the last step, the ANN-based 4-D hyper-chaotic system designed on FPGA has been synthesized and tested using Xilinx ISE Design Suite. The chip statistics have been given after the Place&Route process carried out for the Virtex XC6VHX255T-3FF1155 FPGA chip. The maximum operating frequency of ANN-based 4-D hyper-chaotic system on FPGA has been obtained as 240.861 MHZ.
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    Edge Dedection Application With FPGA Based Sobel Operator
    (Ieee, 2015) Koyuncu, İsmail; Çetin, Özdemir; Katırcıoğlu, Ferzan; Tuna, Murat
    Image processing can be defined as analysis of the images consists of the several steps. The edge detection process that is one of these steps can be performed using a variety of operators. Sobel edge detection operator, is a basic operator, is preferred to use with high noisy images because its corruption is insensible on images. The proposed work presents an edge detection algorithm using Sobel operator based on FPGA architecture. Proposed system is designed using IEEE 754-1985 floating-point standard and VHDL hardware description language. Design is synthesized for Xilinx Virtex-6 FPGA chip with 160 MHz operating frequency. The performance is decreed according chip statistics.
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    Real Time Hardware Implementation of the 3D Chaotic Oscillator which having Golden-Section Equilibra
    (Ieee, 2016) Tuna, Murat; Fidan, Can Bülent; Koyuncu, İsmail; Pehlivan, İhsan
    In this study, the continuous-time, autonomous, 3D chaotic system having golden-section equilibra which is recently presented in the literature is implemented firstly as discrete time on an FPGA. In this design, the 3D chaotic system was programmed in 32-bit IQ-Math (16I-16Q) fixed-point number format using VHDL and Heun algorithm. The designed system has been synthesized and tested, using Xilinx ISE design tool, on Virtex-6 FPGA chip. According to the test results, operation frequency of the FPGA-based new chaotic signal generator is certain as 406.736MHz. In addition, chip statistics and performance results of the new chaotic oscillator are presented after the "Route&Place" processes performed on Xilinx ISE design tool. The chaotic oscillator design realized with fixed-point number format on FPGA has been shown to be use lesser chip hardware and higher operating frequency compared to the floating-point standard.
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    Real Time Implementation of A Novel Chaotic Generator on FPGA
    (Ieee, 2015) Tuna, Murat; Koyuncu, İsmail; Fidan, Can Bülent; Pehlivan, İhsan
    In this study, a new continuous-time autonomous chaotic system has been presented and implemented on FPGA. Presented a new chaotic system has been designed using the IEEE 754-1985 floating-point format and implemented using Heun algorithm with VHDL language. The designed system has been synthesized and tested on Xilinx Virtex-6 FPGA chip. According to the test results, operation frequency of the FPGA-based a new chaotic signal generator is certain as 390 MHz and performance results have been given with chip statistics. In addition, the results obtained from FPGA-based new chaotic generator have been compared with the Matlab-based numerical results and it has been observed that obtained results are successful. By the developed FPGA-based novel chaotic system model, chaos-based various engineering applications such as true random number generation and secure communication system can be performed.