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Öğe An analog circuit design and FPGA-based implementation of the Burke-Shaw chaotic system(Natl Inst Optoelectronics, 2013) Koyuncu, İsmail; Özcerit, Ahmet Turan; Pehlivan, İhsanIn this study, the Burke-Shaw chaotic system has been modeled in three different platforms. In the first stage, the chaotic system has been modeled numerically with the RK5-Butcher algorithm, and the obtained time series and phase portraits are presented. In the second stage, the chaotic system has been modeled with analog circuit components. The results obtained from the numerical modeling confirm the validity of the modeling with analog components. In the final stage, in order to study the RK5-Butcher algorithm, the Burke-Shaw chaotic system has been modeled in VHDL, a hardware description language. The results of the FPGA-based and the numerical modeling results have been compared each other and a sufficient validation score achieved. According to the test results, the operation frequency of the FPGA-based chaotic oscillator is 373.094MHz and it can generate a million-data set in 0.796 seconds.Öğe Chaos-based engineering applications with a 3D chaotic system without equilibrium points(Springer, 2016) Akgül, Akif; Çalgan, Haris; Koyuncu, İsmail; Pehlivan, İhsan; İstanbullu, AyhanThere has recently been an increase in the number of new chaotic system designs and chaos-based engineering applications. In this study, since homoclinic and heteroclinic orbits did not exist and analyses like Shilnikov method could not be used, a 3D chaotic system without equilibrium points was included and thus different engineering applications especially for encryption studies were realized. The 3D chaotic system without equilibrium points represents a new different phenomenon and an almost unexplored field of research. First of all, chaotic system without equilibrium points was examined as the basis and electronic circuit application of the chaotic system was realized and oscilloscope outputs of phase portraits were obtained. Later, chaotic system without equilibrium points was modelled on Labview Field Programmable Gate Array (FPGA) and then FPGA chip statistics, phase portraits and oscilloscope outputs were derived. With another study, VHDL and RK-4 algorithm were used and a new FPGA-based chaotic oscillators design was achieved. Results of Labview-based design on FPGA- and VHDL-based design were compared. Results of chaotic oscillator units designed here were gained via Xilinx ISE Simulator. Finally, a new chaos-based RNG design was achieved and internationally accepted FIPS-140-1 and NIST-800-22 randomness tests were run. Furthermore, video encryption application and security analyses were carried out with the RNG designed here.Öğe Design and Implementation of Chaos Based True Random Number Generator on FPGA(Ieee, 2014) Koyuncu, İsmail; Özcerit, Ahmet Turan; Pehlivan, İhsan; Avaroğlu, ErdinçCurrently, chaotic signal generators is of importance in cryptographic applications and chaotic communication systems. One of the significant field of the chaotic signal oscillators are random number generators. In this paper, an FPGA-based new true random number generator system using discrete-time chaotic signal generator is presented. The system designed incorporates the Sprott 94 G chaotic system based on an FPGA deployed with IEEE 754 standard. In order to produce random bits a quantification process has been performed on the results produced by the chaotic oscillator unit. Furthermore, the XOR method has been determined as restoring function to obtain a true random bit generator. The maximum operating frequency of FPGA-based true random number generator has been able to reach up to 399,383 MHz. The 20,000-bit sequence has been generated by the designed system and they have been saved to the test result file. They have been tested using NIST test suite and FIPS-140-1 standards and successful results have been obtained. It is concluded that the FPGA-based system is able to be used in cryptologic applications.Öğe Design and Implementation of High Speed Artificial Neural Network Based Sprott 94 S System on FPGA(2016) Koyuncu, İsmailFPGA-based embedding system designs have been preferred for industrial applications and prototyping because of the advantages of parallel processing, reconfigurability and low cost. Due to having characteristic structure of the parallel processing of Artificial Neural Networks (ANNs), these systems provide the advantage of speed and performance when they are implemented with FPGA-based hardware. The hardware implementation of transfer functions used for modeling non-linear systems is a challenging problem. Therefore, this problem creates convergence problems. In this paper, non-linear Sprott 94 S system has been modeled using ANNs running on FPGA. All related parameter values and processes are defined with IEEE-754-1985 32-bit single precision floatingpoint number standard. ANN-based Sprott 94 S system design has been developed using VHDL synthesized using Xilinx ISE Design Tools. In test stage, ANN-based Sprott 94 S system has been tested using 3X100 data set and obtained error analysis results have been presented. The constructed design has been performed for Xilinx VIRTEX-6 family XC6VHX255T-3FF1923 FPGA chip using Place&Route process and chip usage statistics have been given. The clock frequency of ANN-based Sprott 94 S system which has pipeline processing scheme has been obtained with the value of 304.534 MHz. Accordingly, the proposed FPGA-based ANN system has produced 3X3.284 billion outputs in 1 second.Öğe Design and Implementation of Neural Networks Neurons with RadBas, LogSig, and TanSig Activation Functions on FPGA(Kaunas Univ Technology, 2012) Şahin, İbrahim; Koyuncu, İsmailI. Sahin, I. Koyuncu. Design and Implementation of Neural Networks Neurons with RadBas, LogSig, and TanSig Activation Functions on FPGA // Electronics and Electrical Engineering. - Kaunas: Technologija, 2012. - No. 4(120). - P. 51-54. Artificial Neural Networks (ANNs) are utilized in several key areas such as prediction, classification, motor control, etc. When high performance is needed, FPGA realizations of the ANNs are preferred. In this study, we designed and implemented a total of 18 different FPGA-based neurons, 2, 4 and 6-input biased and non-biased with each having three different activation functions requiring the calculations of e(x). Our purpose was to show the possibility of implementing neural networks with exponential activation functions on current FPGAs and measure the performance of the neurons. The results showed that up to 10 neurons can fit in to the smallest Virtex-6 and the network can be clocked up to 405MHz. Ill. 6, bibl. 11, tabl. 2 (in English; abstracts in English and Lithuanian).Öğe The design and realization of a new high speed FPGA-based chaotic true random number generator(Pergamon-Elsevier Science Ltd, 2017) Koyuncu, İsmail; Özcerit, Ahmet TuranChaotic systems and chaos-based applications have been commonly used in the fields of engineering recently. The most essential part of them is the chaotic oscillator that has very critical role in some applications such as chaotic communications and cryptography. In this study, Sundarapandian-Pehlivan chaotic system has been modeled and simulated in three distinct platforms to show the advantages of FPGA-based chaotic oscillator with respect to alternative solutions. In the first stage, the chaotic system has been modeled numerically by the help of fourth order of Runge-Kutta (RK4) method. Additionally, phase portraits of the system have been obtained and Lyapunov exponents have been examined. Secondly, the system has been modeled by using PSpice for the implementation of the chaotic system with analog circuit elements. Then, Pspice simulation results have been compared with the numerical outcome to justify the designed model. Furthermore, the chaotic system has been physically confirmed with real analog circuit elements. Signals obtained from the physical system have been verified with both numerical and PSpice results. It has been also modeled by the help of method of RK4 in a hardware description language (VHDL) and the model further has been synthesized and tested for Xilinx Virtex-6 FPGA chip. Finally, the chaotic oscillator designed has been tested for True Random Number Generators (TRNG) and the maximum operating frequency has been achieved as 293 MHz with a speed of 58.76 Mbit/s. Besides, the random bit sets produced by TRNG have been further verified by FIPS-140-1 and NIST-800-22 statistical standards and it has been proved that the proposed design can be used in embedded cryptologic applications. (C) 2016 Elsevier Ltd. All rights reserved.Öğe Edge Dedection Application With FPGA Based Sobel Operator(Ieee, 2015) Koyuncu, İsmail; Çetin, Özdemir; Katırcıoğlu, Ferzan; Tuna, MuratImage processing can be defined as analysis of the images consists of the several steps. The edge detection process that is one of these steps can be performed using a variety of operators. Sobel edge detection operator, is a basic operator, is preferred to use with high noisy images because its corruption is insensible on images. The proposed work presents an edge detection algorithm using Sobel operator based on FPGA architecture. Proposed system is designed using IEEE 754-1985 floating-point standard and VHDL hardware description language. Design is synthesized for Xilinx Virtex-6 FPGA chip with 160 MHz operating frequency. The performance is decreed according chip statistics.Öğe Electronic Circuit Realization and Synchronization Application of Sprott 94 S Chaotic System for Secure Communication Systems(Ieee, 2013) Koyuncu, İsmail; Alçın, Murat; Pehlivan, İhsanIn this paper, the numerical model and electronic circuit model using Pspice of Sprott 94 S system is presented. The chaotic system modelling with electronic circuit elements is realized physically. Besides, the synchronization of Sprott 94 S system is fulfilled using Pspice program. In realized synchronization, Sprott 94 S chaotic oscillators that run on different initial states have been in synchronization with a very short time. The Sprott 94 S system's chaotic oscillator which is designed using analog electronic elements, has been introduced in this paper for the first time. In addition, various signal encryption and secure communication applications can be performed using the electronic circuit model of Sprott 94 S system given in this paper.Öğe FPGA Implementation of RK4 based Van der Pol Oscillator(Turgut Ozal Univ, 2012) Koyuncu, İsmail; Erdoğmuş, PakizeFPGA chips have quite high speed and capacity now. They are also used in several disciplines. For high speed and performance required applications, FPGAs are of great importance since they provide flexible and low-cost solutions. Most of these applications require intensive mathematical operations and the calculations of these mathematical operations are both time consuming and difficult. Differential equations are the biggest part of such applications. This study aims to implement the Van der Pol oscillator on FPGA. In this process, the fourth order Runge-Kutta algorithm was selected as ODE solver. Van der Pol oscillator equations are quite sensitive to the parameter which specifies the nonlinearity and the strength of damping. Van der Pol oscillator's differential equations can have stiff property related to damping parameter. So, implementation performance was tested for different parameter values which make the differential equations non-stiff.Öğe Grafik sistemleri için FPGA cihazlarında çalışmak üzere tasarlanmış matris çarpım motoru(Düzce Üniversitesi, 2008) Koyuncu, İsmail; Şahin, İbrahimBilgisayar grafiklerinde, üç boyutlu (3B) dönüşümlerde, animasyon sahnesindeki dönüşüme uğrayan nesne sayısı ve bu nesneleri tanımlamada kullanılan nokta sayısı arttıkça dönüşümü hesaplamak için çok fazla CPU zamanı gerekmektedir. Sonuçta, özellikle gerçek zamanlı grafik uygulamalarının hesaplanması imkânsız hale gelmektedir. Bu çalışmada, FPGA (Alan Programlanabilir Kapı Dizileri) çiplerini kullanarak üç boyutlu dönüşümleri hızlandırmak için donanım modülleri tasarlanmıştır. Tasarlanan modüller gerçek veri üzerinde işlemler yapılarak test edilmiş ve modüllerin ürettiği sonuçların doğrulanması yapılmıştır. Modüllerin veri işleme hızı değişik bilgisayarlarla karşılaştırılmıştır. Karşılaştırma sonuçları göstermiştir ki, tasarlanan modüller kullanılarak üç boyutlu grafik dönüşümleri 12 kata kadar daha hızlı gerçekleştirilebilmektedir.Öğe Hardware design and implementation of a novel ANN-based chaotic generator in FPGA(Elsevier Gmbh, 2016) Alçın, Murat; Pehlivan, İhsan; Koyuncu, İsmailThis paper presents a novel hardware implementation of Artificial Neural Networks (ANNs) for modeling of the Pehlivan-Uyaroglu Chaotic System (PUCS) on Field Programmable Gate Array (FPGA). There are two main parts in the proposed work. In the first part, a 3-8-3 Feed Forward Neural Network (FFNN) has been created using Matlab R2015a. The training results show that FFNN trained with back propagation algorithm exhibits satisfactory precision for the direct implementation. In the second part, the hardware implementation of the trained network has been carried out. The designed architecture is presented using Very High Speed Integrated Circuits Hardware Description Language (VHDL) and is implemented on a Xilinx Virtex 6 (XC6VCX240T) chip. All related parameters are defined with IEEE 754 single precision floating point number format. For the approximation of Log-Sigmoid transfer function, Xilinx's COordinate Rotation Digital Computer (CORDIC) design has been employed. The design can be used with a clock frequency up to 266.429 MHz. Finally, chip statistics of FPGA and analysis results have been presented. The proposed work have showed that chaotic systems can be successfully modeled using ANNs on FPGA. In future, chaos-based engineering applications can be performed using ANN-based chaotic oscillators on FPGA. (C) 2016 Elsevier GmbH. All rights reserved.Öğe Hybrid pseudo-random number generator for cryptographic systems(Springer, 2015) Avaroğlu, Erdinç; Koyuncu, İsmail; Özer, A. Bedri; Türk, MustafaFor a powerful cryptographic system, high-quality random number streams are essential. Those raw pseudo-random number generators (PRNG) that are used to generate high-quality random numbers have some disadvantages, such as failure to meet the R4 security requirement. Therefore, use of random number sequences generated by these generators in a cryptographic system puts the entire system at risk. This study proposes a new hybrid PRNG by means of an additional input introduced to transition and output functions used in a raw PRNG system in order to eliminate this risk. The additional inputs to the designed system have been implemented via the true random number generator developed by using the Sprott 94 G chaotic system on FPGA. The random number streams obtained from the recommended hybrid structure have been subjected to the NIST 800.22 and FIPS statistical test, which have given good results. According to these results, it has been proved that the recommended hybrid PRNG system meets the R4 security requirement and can be used in cryptographic applications.Öğe Implementation of FPGA-based real time novel chaotic oscillator(Springer, 2014) Koyuncu, İsmail; Özcerit, Ahmet Turan; Pehlivan, İhsanCurrently, chaotic systems and chaos-based applications are commonly used in the engineering fields. One of the main structures used in these applications is the chaos-based signal generators. Chaotic signal generators have an important role, particularly in chaotic communication and cryptology. In this study, the Pehlivan-Wei chaotic system, which is a recently developed chaotic system, has been implemented with FPGA using three distinct algorithms (the Euler, Heun, and RK4) for the first time in literature. Numerical and HDL approaches are implemented by these three algorithms to compare the performance of each model for use in chaotic generators. In addition, the Lyapunov exponents and phase portraits of the system have been extracted for chaos analysis. RMSE analysis has been conducted on the chaotic generators, which are modeled using the Euler, Heun, and RK4 algorithms in order to observe error rates of each numerical algorithm in a comparative aspect. The performance of new chaotic system with various data sets has been analyzed. The operation frequency of the chaotic oscillators synthesized and tested for the Virtex-6 FPGA chip has been able to reach up to 463.688 MHz and the chaotic system has been able to calculate 300,000 data sets in 0.0284 s. However, PC-based algorithm having highest performance score can calculate 300,000 data sets in a period of 75.363 s. A comparison study has been performed on the performance of the FPGA-based and PC-based solutions to evaluate each approach.Öğe A Neuron Library for Rapid Realization of Artificial Neural Networks on FPGA: A Case Study of Rossler Chaotic System(World Scientific Publ Co Pte Ltd, 2017) Koyuncu, İsmail; Şahin, İbrahim; Gloster, Clay; Sarıtekin, Namık KemalArtificial neural networks (ANNs) are implemented in hardware when software implementations are inadequate in terms of performance. Implementing an ANN as hardware without using design automation tools is a time consuming process. On the other hand, this process can be automated using pre-designed neurons. Thus, in this work, several artificial neural cells were designed and implemented to form a library of neurons for rapid realization of ANNs on FPGAbased embedded systems. The library contains a total of 60 different neurons, two-, four- and six-input biased and non-biased, with each having 10 different activation functions. The neurons are highly pipelined and were designed to be connected to each other like Lego pieces. Chip statistics of the neurons showed that depending on the type of the neuron, about 25 selected neurons can be fit in to the smallest Virtex-6 chip and an ANN formed using the neurons can be clocked up to 576.89 MHz. ANN based Rossler system was constructed to show the effectiveness of using neurons in rapid realization of ANNs on embedded systems. Our experiments with the neurons showed that using these neurons, ANNs can rapidly be implemented as hardware and design time can significantly be reduced.Öğe A new module design for 3D graphic transformations using generated floating-point core units(Praise Worthy Prize S.r.l, 2011) Şahin, İbrahim; Koyuncu, İsmailA typical animation scene of a computer animation may include hundreds of mathematically defined objects. Applying Three Dimensional (3D) affine transformations to such scenes requires huge amount of CPU time. In this study, an improved hardware module was designed to speed-up 3D graphic transformations using FPGA (Field Programmable Gate Array) chips. In the module design, for multiplication and addition operations, 32-bit multipliers and adders formed on FPGA fabric by IP CORE Generator tool were utilized. The module was tested and functionally verified. Module's data processing speed was compared to various PCs and to our previous module design. Results showed that, 3D graphic transformations can be speeded-up by factor of up to 40 times using the designed module compared to the PCs. Employing multipliers and adders formed with Xilinx's IP CORE Generator in the module design provided 1.4 times performance gain over our previous module design. © 2011 Praise Worthy Prize S.r.l. - All rights reserved.Öğe Real Time Hardware Implementation of the 3D Chaotic Oscillator which having Golden-Section Equilibra(Ieee, 2016) Tuna, Murat; Fidan, Can Bülent; Koyuncu, İsmail; Pehlivan, İhsanIn this study, the continuous-time, autonomous, 3D chaotic system having golden-section equilibra which is recently presented in the literature is implemented firstly as discrete time on an FPGA. In this design, the 3D chaotic system was programmed in 32-bit IQ-Math (16I-16Q) fixed-point number format using VHDL and Heun algorithm. The designed system has been synthesized and tested, using Xilinx ISE design tool, on Virtex-6 FPGA chip. According to the test results, operation frequency of the FPGA-based new chaotic signal generator is certain as 406.736MHz. In addition, chip statistics and performance results of the new chaotic oscillator are presented after the "Route&Place" processes performed on Xilinx ISE design tool. The chaotic oscillator design realized with fixed-point number format on FPGA has been shown to be use lesser chip hardware and higher operating frequency compared to the floating-point standard.Öğe Real Time Implementation of A Novel Chaotic Generator on FPGA(Ieee, 2015) Tuna, Murat; Koyuncu, İsmail; Fidan, Can Bülent; Pehlivan, İhsanIn this study, a new continuous-time autonomous chaotic system has been presented and implemented on FPGA. Presented a new chaotic system has been designed using the IEEE 754-1985 floating-point format and implemented using Heun algorithm with VHDL language. The designed system has been synthesized and tested on Xilinx Virtex-6 FPGA chip. According to the test results, operation frequency of the FPGA-based a new chaotic signal generator is certain as 390 MHz and performance results have been given with chip statistics. In addition, the results obtained from FPGA-based new chaotic generator have been compared with the Matlab-based numerical results and it has been observed that obtained results are successful. By the developed FPGA-based novel chaotic system model, chaos-based various engineering applications such as true random number generation and secure communication system can be performed.Öğe The Evaluation of SCUBE-1 and sCD40L Levels in Diabetic Nephropathy(Düzce Üniversitesi, 2019) Karakaş, Hilal; Eren, Mehmet Ali; Koyuncu, İsmail; Kırhan, İdris; Sabuncu, TevfikAim: There is a close link between diabetic nephropathy and atherosclerotic heart disease. We aimed to evaluate the changes of SCUBE-1 and sCD40L, which play role in the course of atherosclerosis, with the progression of nephropathy in patients with type 2 diabetes.Material and Methods: Thirty healthy subjects (group 1) and 74 patients with type 2 diabetes (divided into 3 groups as normal albuminuria group (group 2, n=33), moderately increased albuminuria group (group 3, n=22) and severely increased albuminuria group (group 4, n=19)) were enrolled in the study. Plasma SCUBE-1 and sCD40L levels were measured using the enzyme-linked immunosorbent assay technique.Results: Mean SCUBE-1 levels were significantly higher in group 4 compared to group 1 and group 2 (p=0.005 and p=0.014, respectively) and in group 3 compared to group 1 and group 2 (p=0.011 and p=0.028, respectively). Mean sCD40L levels were significantly higher in group 4 than in other three groups (all p lt;0.001), and in group 3 than in group 1 and group 2 (p=0.001 and p=0.016, respectively). Furthermore, SCUBE-1 level was positively correlated with total cholesterol level (r=0.212, p=0.031) and triglyceride (r=0.194, p=0.049). Likewise, sCD40L level was positively correlated with only creatinine level (r=0.297, p=0.002).Conclusion: SCUBE-1 and sCD40L levels increased with the progression of nephropathy in type 2 diabetes. This increment suggested that SCUBE-1 and sCD40L may play key role in the course of atherosclerosis due to diabetic nephropathy and, diabetic nephropathy may affect the levels of these parameters.
